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ESP32-H2 Pinout Cheat Sheet

Hardware Overview

The ESP32-H2 is a low-power, single-core RISC-V microcontroller with integrated 2.4 GHz Bluetooth Low Energy and IEEE 802.15.4 wireless connectivity.

It supports Zigbee, Thread and Matter applications through appropriate protocol stacks. Unlike the ESP32-C3 and ESP32-C6, the ESP32-H2 does not contain a Wi-Fi radio.

This reference covers the ESP32-H2 QFN32 chip pinout, including physical package pin numbers, GPIO functions, ADC channels, USB, UART, JTAG, boot strapping and low-power pins.

Module and development-board connector assignments may differ.

The 19 GPIO signals exposed by the QFN32 package are not numbered consecutively. The GPIO numbering space is larger than the number of available physical pins.

Complete ESP32-H2 QFN32 Pinout

The following table uses physical package pin numbers, not development-board connector positions.

Important: Package pin numbers and GPIO numbers are different. Package pin 22 is GPIO23, for example.

The GPIO numbers not bonded out in this package must not be assumed available merely because they exist in a software GPIO numbering range.

GPIO Function Reference

General-Purpose GPIO Assignments

GPIO signals may be routed to compatible peripherals through the GPIO matrix.

Direct IO MUX assignments can provide more appropriate routing for timing-sensitive functions than general GPIO matrix routing.

Boot Strapping Pins

The ESP32-H2 uses three strapping pins.

Strapping pins are sampled during reset. Their states must meet the requirements of the desired configuration.

Boot Mode Selection

Normal SPI boot is selected with GPIO9 high.

Joint download boot requires GPIO8 high and GPIO9 low. This mode supports UART and USB Serial/JTAG downloading.

Boot warning: Do not connect an external peripheral that holds GPIO9 low during normal startup.

A conventional BOOT button can pull GPIO9 low, but the GPIO8 state must also satisfy the download-mode requirement.

Strapping Timing

GPIO25 selects the JTAG signal source subject to eFuse configuration. It must not be left in an uncontrolled state when its strapping function is required.

ADC Pinout

The ESP32-H2 has one 12-bit SAR ADC with five external input channels.

GPIO2–5 are also used for external JTAG debugging.

ADC restrictions:

• Use an appropriate ADC attenuation setting.
• Do not exceed the permitted analogue input-voltage range.
• Account for source impedance and settling time.
• Use calibration for voltage measurements requiring improved accuracy.
• Avoid strong digital interference near sensitive analogue inputs.
• Do not assume ADC readings are accurate across the entire supply-voltage range.

ADC input accuracy is not determined by resolution alone. The reference, input attenuation, calibration and PCB design affect measurement error.

Analogue Comparator Pins

The ESP32-H2 includes an analogue pad voltage-comparator function.

The comparator permits detection of an analogue relationship between its input and reference under supported configurations.

These pins can also be used as ordinary GPIOs when the analogue comparator is not enabled.

The comparator is not a substitute for the SAR ADC when a numerical voltage measurement is required.

USB Serial/JTAG Pinout

The ESP32-H2 includes a native USB Serial/JTAG controller.

The native USB controller supports serial communication, firmware downloading and JTAG debugging.

It is not a general-purpose USB OTG controller.

USB Restrictions

• GPIO26 and GPIO27 are assigned to the USB Serial/JTAG interface by default.
• Reassigning either pin can disable native USB communication.
• USB D+ and D− require appropriate routing and protection.
• USB VBUS must be handled according to the development board’s power architecture.
• USB HID, USB host and arbitrary USB device-class applications are not provided by this controller.

Some development boards additionally provide an external USB-to-UART converter. Such a converter is separate from the ESP32-H2 native USB functionality.

UART Pin Assignments

The ESP32-H2 provides two UART controllers.

UART0 Default Pins

UART0 is commonly used for the ROM console, serial logging and firmware downloading.

Other UART signals can be routed to suitable GPIOs using the GPIO matrix.

UART Engineering Notes

• UART operates at the GPIO logic voltage.
• Do not connect RS-232 voltage levels directly.
• Use a suitable level converter for RS-232 interfaces.
• Ensure TX and RX are crossed between communicating devices.
• Connect grounds where required.
• Check console configuration before reassigning GPIO23 and GPIO24.

If UART0 is required for diagnostics, reserve its default pins during initial hardware development.

External JTAG Debugging

The ESP32-H2 supports external JTAG through GPIO2–5.

These GPIOs also support ADC inputs.

Using them for analogue measurements may prevent simultaneous use of the corresponding external JTAG connections.

USB Serial/JTAG provides an alternative debugging path.

JTAG source selection depends on GPIO25 strapping and relevant eFuse settings.

SPI2 Pin Reference

The ESP32-H2 contains an application SPI controller, SPI2, separate from the internal flash interfaces.

Native IO MUX Assignments

SPI2 may also use GPIO matrix routing where supported.

When choosing SPI pins, consider the conflicts with JTAG, ADC, UART0, USB and boot-strapping requirements.

For a basic four-wire SPI connection, the signals required are SCLK, MOSI, MISO and CS. The actual data-direction naming depends on the controller mode and software framework.

I2C and Other Peripheral Routing

The GPIO matrix allows flexible signal assignment for several application peripherals.

I2C Wiring

SDA and SCL require pull-up resistors to the correct logic supply.

A common starting point for a short 3.3 V bus is 4.7 kΩ, but the resistor value must satisfy the bus capacitance, rise-time and speed requirements.

GPIOs used for boot strapping should be avoided where attached pull-ups or peripherals could interfere with reset levels.

TWAI

TWAI is Espressif’s CAN-compatible controller.

The controller provides protocol-level functionality, but an external CAN transceiver is required for connection to a physical CAN bus.

Do not connect the GPIO TX and RX signals directly to CAN_H and CAN_L.

Low-Power GPIO Reference

The ESP32-H2 has a dedicated low-power subsystem.

GPIO13 and GPIO14 share their pads with the optional 32 kHz crystal interface.

The LP GPIO group can operate in supported low-power modes, including deep sleep.

Other GPIOs may have restrictions when the main digital power domain is disabled.

Deep-Sleep Considerations

• Select wake-up sources supported by the ESP32-H2.
• Use appropriate GPIO pull configurations.
• Avoid external circuits that create excessive leakage.
• Check the behaviour of GPIOs when their power domain is disabled.
• Account for the internal flash, regulators and external peripherals.
• Verify actual board current rather than relying only on the SoC figure.

The datasheet specifies a deep-sleep current of approximately 7 µA under its defined measurement conditions. A complete development board may consume substantially more.

Wireless Interface Considerations

The ESP32-H2 integrates two wireless technologies.

The integrated 2.4 GHz antenna interface appears on package pin 32, ANT.

ANT is an RF connection and cannot be used as an ordinary GPIO.

A custom PCB requires the correct RF matching network, controlled-impedance routing and suitable antenna design.

Wireless coexistence requires scheduling because Bluetooth LE and IEEE 802.15.4 share radio resources.

GPIO Selection Quick Reference

Pin allocation priority: Reserve boot, USB, UART debugging and RF requirements first. Then allocate application GPIOs and analogue inputs.

Common Pinout Problems

Module and Development Board Restrictions

The bare ESP32-H2 package pinout must not be confused with the header layout of a development board.

In-package flash is already provided by supported ESP32-H2 variants. The external application GPIO count should not be confused with internal memory-interface signals.

Some development-board pins are connected to onboard components and may not be freely available.

Electrical and PCB Design Notes

• ESP32-H2 GPIOs are intended for their specified 3.3 V supply domains.
• GPIOs are not general-purpose 5 V-tolerant inputs.
• Respect the recommended operating conditions, not merely absolute maximum ratings.
• Do not drive motors, relays or substantial loads directly from GPIO pins.
• Use appropriate transistor or driver circuits.
• Provide the required supply decoupling close to the chip.
• Do not leave CHIP_EN floating.
• Ensure strapping levels are valid during reset.
• Keep analogue signals away from high-current switching traces.
• Maintain proper USB differential routing.
• Protect the RF antenna path from unsuitable PCB routing and nearby interference.
• Check GPIO configuration and power-domain behaviour when entering deep sleep.

The final GPIO assignment must be checked against the exact ESP32-H2 silicon variant, module datasheet, PCB schematic and selected ESP-IDF configuration.

 

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